vbus54ed-fbl www.vishay.com vishay semiconductors rev. 1.0, 15-aug-11 1 document number: 82414 for technical questions, contact: esdprotection@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 4-line bus-port esd protection - flow through design marking (example only) dot = pin 1 marking yy = type code (see table below) xx = date code features ? compact llp2510-10l package ? low package height < 0.6 mm ? 4-line esd-protection ? low leakage current i r < 0.1 a ? low load capacitance c d = 0.6 pf ? ideal for high speed data line like - hdmi, displayport, esata - usb, 1394/firewire ? esd-protection acc. iec 61000-4-2 15 kv contact discharge 15 kv air discharge ? soldering can be checked by standard vision inspection. no x-ray necessary ? e4 - precious metal (e.g. ag , au, nipd, nipdau) (no sn) ? compliant to rohs directive 2002/95/ec and in accordance to weee 2002/96/ec note ** please see document vishay material category policy: www.vishay.com/doc?99902 22551 nc. g nd g nd d2+ 12345 9876 nc. nc. nc. d2- d1+ d1- 22552 10 yyxx 20720 ordering information device name ordering code taped units per reel (8 mm tape on 7" reel) minimum order quantity vbus54ed-fbl VBUS54ED-FBL-G4-08 3000 15 000 package data device name package name type code weight molding compound flammability rating moisture sensitivity level soldering conditions vbus54ed-fbl llp2510-10l l5 3.9 mg ul 94 v-0 msl level 1 (according j-std-020) 260 c/10 s at terminals absolute maximum ratings parameter test conditions symbol value unit peak pulse current acc. iec 61000-4-5; t p = 8/20 s; single shot i ppm 2a peak pulse power acc. iec 61000-4-5; t p = 8/20 s; single shot p pp 25 w esd immunity contact discharge acc. iec 61000-4-2; 10 pulses v esd 15 kv air discharge acc. iec 61000-4-2; 10 pulses v esd 15 kv operating temperature junction temperature t j - 40 to + 125 c storage temperature t stg - 55 to + 150 c
vbus54ed-fbl www.vishay.com vishay semiconductors rev. 1.0, 15-aug-11 2 document number: 82414 for technical questions, contact: esdprotection@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 note ? ratings at 25 c, ambient temperature unless otherwise specified application note the vbus54ed-fbl is a four-line esd-protection device with the characteristic of a z-diode with a high esd-immunity and a very low capacitance which makes it usable for high frequency applications like usb2.0, usb3.0 or hdmi. with the vbus54ed-fbl four high speed data lines can be protected against transient voltage signals like esd (electro static discharge). connected to the data line (pin 1, 2 and pin 4, 5) an d to ground (pin 3 and 8) nega tive transients will be clamped close below the ground level while positi ve transients will be clamped close abov e the 5.5 v working range. the clamping behaviour of the vbus54ed-fbl is bidirectional but asymmetrical ( bias ) and so it offers the best protection for applications running up to 5.5 v. pin configuration: ? pin 3 and 8 are internally shorted and have to be connected to ground ? pin 1, 2 and 4, 5 are the inputs for the data lines d 1+ and d 1- and d 2+ and d 2- ? pin 6, 7 and 9, 10 are not connected internally flow through design modern digital transmission lines can be clocked up to 480 mbit/s (usb2.0) or 1.65 gbit/s (hdmi). at such high data rates the transmission lines like cables or the line traces on the pcbs have to be very homogeneous regarding their surge impedance. th is requires well defined trace dime nsions as trace width and distance which have to be calculated depending on the requested surge impedance (e.g. 50 ? ) and the pcb material and layer dimensions. any device connected to the data lines - like esd-protection devi ces - have to be connected with minimal changes in these trace dimensions and distances. with the package in the so called flow through design this is possible. the lines are running straight along the pcb while th e vbus54ed-fbl is placed on top without any vias or loops. electrical characteristics vbus54ed-fbl (pin 1, 2, 4 or 5 to pin 3) parameter test conditions/remarks symbol min. typ. max. unit protection paths number of li nes which can be protected n channel --4lines reverse stand-off voltage v rwm --5.5v reverse voltage at i r = 0.1 a v r 5.5 6.3 7.5 v reverse current at v r = v rwm = 5.5 v i r - 0.02 0.1 a reverse breakdown voltage at i r = 1 ma v br 6.9 7.5 8.7 v clamping voltage at i pp = 1 a; acc. iec 61000-4-5 v c -9.111v at i pp = 2 a; acc. iec 61000-4-5 v c - 10.3 12.5 v forward clamping voltage at i f = 1 a; acc. iec 61000-4-5 v f -1.92.2v at i f = 2 a; acc. iec 61000-4-5 v f -2.53.1v line capacitance at v r = 0 v; f = 1 mhz c d -0.70.8 pf at v r = 3.3 v; f = 1 mhz - 0.6 0.8 nc. g nd g nd d2+ 12345 9876 nc. nc. nc. d2- d1+ d1- 22552 10 matched pair matched pair 12345 10 9 8 7 6 u s b / hdmi interface d2+ d2- d1+ d1- g nd d2+ d2- d1+ d1- i/o port connector ------ 22553
vbus54ed-fbl www.vishay.com vishay semiconductors rev. 1.0, 15-aug-11 3 document number: 82414 for technical questions, contact: esdprotection@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 typical characteristics (t amb = 25 c, unless otherwise specified) fig. 1 - esd discharge current wave form acc. iec 61000-4-2 (330 ? /150 pf) fig. 2 - 8/20 s peak pulse current wave form acc. iec 61000-4-5 fig. 3 - typical capacitance c d vs. reverse voltage v r fig. 4 - typical forward current i f vs. forward voltage v f fig. 5 - typical reverse voltage v r vs. reverse current i r fig. 6 - typical peak clamping voltage v c vs. peak pulse current i pp 0 % 20 % 40 % 60 % 80 % 100 % 120 % - 10 0 10 20 30 40 50 60 70 80 90 100 time (ns) discharge current i esd rise time = 0.7 ns to 1 ns 53 % 27 % 20557 0 % 20 % 40 % 60 % 80 % 100 % 010203040 time (s) i ppm 20 s to 50 % 8 s to 100 % 20548 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0123456 c d pf f = 1 mhz pin 1, 2, 4 or 5 to pin 3 and 8 s econd pin at 0 v s econd pin at 5 v s econd pin at 3.3 v 22554 v r in (v) 0.001 0.01 0.1 1 10 100 0.5 0.6 0.7 0.8 0.9 1 1.1 22555 v f (v) i f (ma) bia s -mode 0 1 2 3 4 5 6 7 8 0.01 0.1 1 10 100 1000 10 000 pin 1, 2, 4 or 5 to pin 3 22556 i r (a) v r (v) - 6 - 4 - 2 0 2 4 6 8 10 12 14 0123 v c pin 1, 2, 4 or 5 to pin 3 (rever s e) pin 3 to pin 1, 2, 4 or 5 (forward) mea s ured acc. iec 61000-4-5 (8/20 s - wave form) i pp (a) v c (v)
vbus54ed-fbl www.vishay.com vishay semiconductors rev. 1.0, 15-aug-11 4 document number: 82414 for technical questions, contact: esdprotection@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 7 - typical clamping performance at 8 kv contact discharge (acc. iec 61000-4-2) fig. 8 - typical clamping performance at 8 kv contact discharge (acc. iec 61000-4-2) fig. 9 - typical peak clamping voltage at esd contact discharge (acc. iec 61000-4-2) - 20 0 20 40 60 80 100 - 10 0 10 20 30 40 50 60 70 80 90 t (ns) v c-esd (v) 22558 acc. iec 61000-4-2 + 8 kv contact discharge - 120 - 100 - 80 - 60 - 40 - 20 0 20 - 10 0 10 20 30 40 50 60 70 80 90 t (ns) v c-esd (v) 22559 acc. iec 61000-4-2 - 8 kv contact discharge - 40 - 30 - 20 - 10 0 10 20 30 40 50 60 0 5 10 15 20 clamping voltage mea s ured after 30 n s acc. iec 61000-4-2 contact di s charge v e s d (kv) v c-e s d (v)
vbus54ed-fbl www.vishay.com vishay semiconductors rev. 1.0, 15-aug-11 5 document number: 82414 for technical questions, contact: esdprotection@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 package dimensions in millimeters: llp2510-10l foot print recommendation: created - date: 08. july 2011 document no.: s 8-v-3906.04-027 (4) package = chip dimen s ion s in mm s older re s i s t ma s k s older pad 0.5 0.25 4 x 0.5 = 2 0.5 0.35 pin 1 marking b e l a1 a3 pin 1 identication chamfer d e millimeter s a a1 a3 d e e l min. nom. max. 0.50 2.45 0.95 0.30 0.55 0.15 2.50 1.00 0.50 0.35 0.60 0,05 2.55 1.05 0.40 0.00 - -- b 0.15 0.20 0.25 -- l a 1 0.15 22587 llp2510 top view pad layout - view from top s een at bottom s ide pin 1 - location s 8-v-3906.04-029 (4) date: 07.07.2011 22588
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